The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

For advanced technologies, the industry is seeing very complicated silicon defect types and defect distribution. One consequence is that scan chain diagnosis becomes more difficult. To improve the ...

To ensure customers receive high-quality products, engineers must consider testing strategies before they even think about a schematic diagram. These days, most engineers realize boundary scan ...

Scan insertion to improve test coverage and reduce test pattern volume is very common in today’s DFT tools. All of the major ATPG tool vendors (Synopsys, Cadence, and Mentor) offer this approach in ...

IC designers now have a powerful weapon in the struggle against rising test costs: commercially available EDA solutions that provide fast and effective means to implement scan compression on-chip. By ...

For more than four decades, scan technology has somehow eluded the radar screen of the IC test industry. As test continues to evolve and make significant newsworthy changes, scan has maintained a ...

"Scan chains provide a window into the chip." - Yervant Zorian, CTO of Virage Logic. "It's well known that scan chains are a major source of vulnerability in embedded systems." - Srinivas Ravi, ...